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M40Z111 M40Z111w nvram controller for up to two lpsram august 1998 1/12 convert low power srams into nvrams precision power monitoring and power switching circuitry automatic write-protection when v cc is out-of-tolerance choice of supply voltages and power-fail deselect voltages: M40Z111: v cc = 4.5v to 5.5v ths = v ss 4.5v v pfd 4.75v ths = v out 4.2v v pfd 4.5v M40Z111w: v cc = 3.0v to 3.6v ths = v ss 2.8v v pfd 3.0v v cc = 2.7v to 3.3v ths = v out 2.5 v pfd 2.7v less than 15ns chip enable access propagation delay (for 5.0v device) packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) soic package provides direct connection for a snaphat top which contains the battery description the M40Z111/111w nvram controller is a self- contained device which converts a standard low- power sram into a non-volatile memory. a precision voltage reference and comparator monitors the v cc input for an out-of-tolerancecon- dition. ai02238 ths v cc M40Z111 M40Z111v e con v ss e v out figure 1. logic diagram ths threshold select input e chip enable input e con conditioned chip enable output v out supply voltage output v cc supply voltage v ss ground table 1. signal names snaphat (sh) battery 28 1 soh28 (mh)
ai02239 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 nc nc nc nc v cc nc v cc nc nc nc nc nc nc nc e nc nc nc nc nc ths nc v ss e con nc nc v out v cc M40Z111 M40Z111v figure 2. soic pin connections warning: nc = not connected. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off) snaphat soic 40 to 85 55 to 125 c t sld (2) lead solder temperature for 10 seconds 260 c v io input or output voltages 0.3 to v cc +0.3 v v cc supply voltage 0.3 to 7 v i o output current 20 ma p d power dissipation 1 w notes: 1. stresses greater than those listed under oabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions ab ove those indicated in the operational section of this specification is not implied. exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. soldering temperature not to exceed 260 c for 10 seconds (total thermal budget not to exceed 150 c for longer than 30 seconds). caution: negative undershoots below 0.3 volts are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. table 2. absolute maximum ratings (1) when an invalid v cc condition occurs, the condi- tioned chip enable (e con ) output is forced inactive to write-protect the stored data in the sram. during a power failure, the sram is switched from the v cc pin to the lithium cell within the snaphat to provide the energy required for data retention. on a subsequent power-up, the sram remains writeprotected until a valid powerconditionreturns. the 28 pin 330mil soic provides sockets with gold plated contacts at both ends for direct connection to a separate snaphat housing containing the battery. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow preventspotential batterydamagedue to the high temperatures required for device surface- mounting. the snaphat housing is keyed to pre- vent reverse insertion. the soic and battery packages are shipped separately in plastic anti- static tubes or in tape & reel form. for the 28 lead soic, the battery package (i.e. snaphat) part number is om4z28-br00sh1o or om4z32- br00sh1o (see table 7). operation the M40Z111/111w, as shown in figure 4, can control up to two standard low-power srams. these srams must be configured to have the chip enable input disable all other input signals. most slow, low-power srams are configured like this, however many fast srams are not. during normal operating conditions, the conditioned chip enable (e con ) output pin follows the chip enable (e) input pin with timing shown in table 6. an internal switch connects v cc to v out . this switch has a voltage drop of less than 0.3v (i out1 ). description (cont'd) 2/12 M40Z111, M40Z111w
when v cc degrades during a power failure,e con is forced inactive independentof e. in thissituation, the sram is unconditionallywrite protected as v cc falls below an out-of-tolerance threshold (v pfd ). thepower fail detectionvalue associated with v pfd is selected by the ths pin and is shown in table 5. (note: ths pin must be connected to either v ss or v out ). if chip enable access is in progress during a powerfail detection,that memory cycle continues to completion before the memory is write protected. if the memory cycle is not terminated within time t wp ,e con is unconditionally driven high, write pro- tecting the sram. a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the sram's contents. at voltagesbelow v pfd (min), the user can be assured the memory will be write protected provided the v cc fall time exceeds t f . as v cc continues to degrade, the internal switch disconnects v cc and connects the internal battery to v out . this occurs at the switchover voltage (v so ). below the v so , the battery provides a volt- age v ohb to the sram and can supply current i out2 (see table 5). when v cc rises above v so , v out is switched back to the supplyvoltage.output e con is held inactive for t er (200ms maximum) after the power supply has reached v pfd , inde- pendent of the e input, to allow for processor stabilization (see figure 6). data retention lifetime calculation most low power srams on the market today can be used with the M40Z111/111w nvram control- ler. there are, however some criteria which should be used in making the final choice of which sram to use. the sram must be designed in a way where the chip enable input disables all other in- puts to the sram. this allows inputs to the M40Z111/111wand srams to be don't care once v cc falls below v pfd (min). the sram should also guarantee data retention down to v cc =2.0v. the chip enable access time must be sufficient to meet the system needs with the chip enable propagation delays included. if dataretention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular srams being evaluated. most srams specify a data retention current at 3.0v. manufacturersgenerally specify a typical condition for room temperature along with a worst case condition(generallyat elevatedtemperatures).the system level requirements will determine the choice of which value to use. the data retention current value of the srams can then be added to the i ccdr value of the M40Z111/111wto determine the total current requirements for data retention. the available battery capacity for the snaphat of your choice can then be divided by this current to determine the amount of data retention available (see table 7). for more information on battery storage life refer to the application note an1012. ai02394 v cc e e con v ss v out v cc cmos sram x8 or x16 3.3v or 5v ths e 0.1 m f 0.1 m f M40Z111 thereshold 1n5817 or mbr5120t3 figure 3. hardware hookup 3/12 M40Z111, M40Z111w
v cc noise and negative-going tran- sients i cc transients, including those produced by output switching, can produce voltage fluctuations, result- ing in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy, which stabilizes the v cc bus. the energy stored in the bypass capacitorswill be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic bypass capacitor value of 0.1 m f (as shown in figure 4) is recommended in order to provide the needed filtering. in addition to tran- sients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, st recommends connecting a schottky di- ode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for throughhole and mbrs120t3 is recommendedfor surface mount. symbol parameter test condition min max unit c in input capacitance v in =0v 8 pf c out (2) output capacitance v out =0v 10 pf note: 1. sampled only, not 100% tested. 2. outputs deselected. table 4. capacitance (1) (t a =25 c; f = 1mhz) input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v note that output hi-z is defined as the point where data is no longer driven. table 3. ac measurement condition ai02326 c l = 100pf or 5pf c l includes jig capacitance 645 w device under test 1.75v figure 4. ac testing load circuit 4/12 M40Z111, M40Z111w
symbol parameter test condition min typ max unit i li (1) input leakage current 0v v in v cc 1 m a i lo (1) output leakage current 0v v out v cc 1 m a i cc supply current outputs open 3 6 ma v il input low voltage 0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 4.0ma 0.4 v v oh output high voltage i oh = 2.0ma 2.4 v v ohb v oh battery back-up i out2 = 1.0 m a 2.0 2.9 3.6 v i out1 v out current (active) v out >v cc 0.3 160 ma v out >v cc 0.2 100 ma i out2 v out current (battery back-up) v out >v bat 0.2 100 m a i ccdr data retention mode current 150 na ths threshold select voltage v ss v out v v pfd power-fail deselect voltage (ths = 0) 4.5 4.6 4.75 v power-fail deselect voltage (ths = 1) 4.2 4.35 4.5 v v so battery back-up switchover voltage 3.0 v note: 1. outputs deselected. table 5a. dc characteristics for M40Z111 (t a = 0 to 70 c; v cc = 4.5v to 5.5v) 5/12 M40Z111, M40Z111w
symbol parameter test condition min typ max unit i li (1) input leakage current 0v v in v cc 1 m a i lo (1) output leakage current 0v v out v cc 1 m a i cc supply current outputs open 2 4 ma v il input low voltage 0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 4.0ma 0.4 v v oh output high voltage i oh = 2.0ma 2.4 v v ohb v oh battery back-up i out2 = 1.0 m a 2.0 2.9 3.6 v i out1 v out current (active) v out >v cc 0.3 100 ma v out >v cc 0.2 65 ma i out2 v out current (battery back-up) v out >v bat 0.2 100 m a i ccdr data retention mode current 150 na ths threshold select voltage v ss v out v v pfd power-fail deselect voltage (ths = 0) 2.8 2.9 3.0 v power-fail deselect voltage (ths = 1) 2.5 2.6 2.7 v v so battery back-up switchover voltage 3.0v pfd , 100mv v note: 1. outputs deselected. table 5b. dc characteristics for M40Z111w (t a = 0 to 70 c; v cc = 3v to 3.6v or 2.7v to 3.3v) 6/12 M40Z111, M40Z111w
symbol parameter min max unit t f (1) v pfd (max) to v pfd (min) v cc fall time 300 m s t fb (2) v pfd (min) to v so v cc fall time 10 m s t r v pfd (min) to v pfd (max) v cc rise time 10 m s t edl chip enable propagation delay M40Z111 15 ns M40Z111w 20 ns t edh chip enable propagation delay M40Z111 10 ns M40Z111w 20 ns t er chip enable recovery 40 200 ms t wp write protect time 40 150 m s notes :1.v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 m s after v cc passes v pfd (min). 2. v pfd (min) to v so fall time of less than t fb may cause corruption of ram data. table 6. power down/up ac characteristics (t a = 0 to 70 c) ai02396 v cc e e con tf tfb v ohb v pfd (max) v pfd (min) v so twpt v pfd figure 5. power down timing 7/12 M40Z111, M40Z111w
ai02397 v cc e e con tr ter v ohb v pfd (max) v pfd (min) v so v pfd tedl tedh figure 6. power up timing part number description package m4z28-br00sh1 lithium battery (50mah) snaphat sh m4z32-br00sh1 lithium battery (130mah) snaphat sh table 7. battery table 8/12 M40Z111, M40Z111w
ordering information scheme note: 1. the soic package (soh28) requires the battery package (snaphat) which is ordered separately under the part number om4zxxbr00sh1o in plastic tube or om4zxx-br00sh1tro in tape & reel form. caution: do not place the snaphat battery package om4zxx-br00sh1o in conductive foam since will drain the lithium button-cell battery. for a list of available options (package, etc...)or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. supply voltage and write protect voltage 111 v cc = 4.5v to 5.5v ths = v ss 4.5v v pfd 4.75v ths = v out 4.2v v pfd 4.5v 111w v cc = 3.0v to 3.6v ths = v ss 2.8v v pfd 3.0v v cc = 2.7v to 3.3v ths = v out 2.5 v pfd 2.7v package mh (1) soh28 temp. range 1 0 to 70 c shipping method for soic blank tubes tr tape & reel example: M40Z111w mh 1 tr 9/12 M40Z111, M40Z111w
symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 0.050 eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n28 28 cp 0.10 0.004 soh28 - 28 lead plastic small outline, battery snaphat soh e n d c l a1 a 1 h a cp be a2 eb drawing is not to scale. 10/12 M40Z111, M40Z111w
sh a1 a d e ea eb a2 b l a3 symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 sh - snaphat housing for 28 lead plastic small outline drawing is not to scale. 11/12 M40Z111, M40Z111w
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. spec ifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved ? snaphat is a registered trademark of stmicroelectronics stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 12/12 M40Z111, M40Z111w

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